The TMS320VC5402PGE100 fixed-point digital signal processor (DSP) is based on an improved Harvard architecture, which has a program memory bus and three data memory buses. The basis of the DSP's operational flexibility and speed is a highly specialized instruction set. Separate program space and data space allow simultaneous access to program instructions and data, thereby providing a high degree of parallelism. In addition, data can be transferred between data space and program space.
1. Advanced multi-bus architecture with three independent 16-bit data memory buses and one program memory bus.
2. Exponential encoder, which can calculate the exponential value of the 40-bit accumulator value in a single cycle.
3. Two address generators with eight auxiliary registers and two auxiliary register arithmetic units (ARAU).
4. Instructions with 32-bit longword operands.
5. Based on the simulation logic of on-chip scan, IEEE Std 1149.1 (JTAG) boundary scan logic.
|Category||Integrated Circuit Embedded-DSP (Digital Signal Processor)|
|Interface||Host Interface, McBSP|
|Non-volatile memory||ROM (8kB)|
|Working temperature||-40°C ~ 100°C (TC)|
|Mounting type||surface mount|
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